Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

Keywords: SRAM Dynamic back-gate design FinFET Robust Low power a b s t r a c t In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads , an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. To maximize the density, SRAM cells are realized using minimum sized transistors in each technology [1]. On the other hand, the shrinkage of the technology feature size to nano-scale regime has adversely impacted the SRAM yield due to uncertainty in the device parameters induced by process variations. In addition, in this regime, short channel effects more severely deteriorate the performance of the SRAM cells. To overcome these problems, new device structures may be invoked. Among them, double gate transistors have superior short channel characteristics and better immunity to process variations when compared to conventional bulk CMOS transistors. These originate from the use of a thin silicon film, lightly doped channel, and two gates for a better channel control [2]. Among double gate transistors, FinFET structure is one of the promising devices thanks to similarity of its fabrication process to that of the planar bulk CMOS [3]. Two gates of FinFET can be tied together or used independently. The independent use …